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cy62128ev30 mobl ? automotive 1-mbit (128 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-65528 rev. *a revised june 27, 2011 1-mbit (128 k 8) static ram features very high-speed: 45 ns temperature ranges: ? automotive-a: ?40 c to +85 c ? automotive-e: ?40 c to +125 c wide voltage range: 2.2 v to 3.6 v pin compatible with cy62128dv30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 4 ? a ultra low active power ? typical active current: 1.3 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2, and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power offered in pb-free 32-pin small outline integrated circuit (soic), 32-pin thin small outline package (tsop) type i, and 32-pin stsop packages functional description the cy62128ev30 is a high performance cmos static ram module organized as 128k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. placing the device in standby mode reduces power consumption by more than 99 percent when deselected (ce 1 high or ce 2 low). the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or a write operation is in progress (ce 1 low and ce 2 high and we low). to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. data on the eight i/o pins is then written into the location specified on the address pin (a 0 through a 16 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. a 0 i/o 0 i/o 7 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 12 sense amps power down we oe a 13 a 14 a 15 a 16 row decoder column decoder 128k x 8 array input buffer a 10 a 11 ce 1 ce 2 logic block diagram [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 2 of 18 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 pin definitions .................................................................. 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 6 thermal resistance .......................................................... 6 ac test loads and waveforms ....................................... 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching characteristics ................................................ 8 switching waveforms ...................................................... 9 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 16 document conventions ................................................. 16 units of measure ....................................................... 16 document history page ................................................. 17 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc solutions ......................................................... 18 [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 3 of 18 pin configuration figure 1. 32-pin stsop [1] figure 2. 32-pin tsop i [1] figure 3. 32-pin soic [1] a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe top view (not to scale) 30 28 29 31 24 19 23 22 21 20 18 13 17 16 15 14 11 12 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce 1 a 11 a 5 9 10 32 1 2 3 4 5 6 7 8 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 26 25 26 27 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce 1 a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view 12 13 29 32 31 30 16 15 17 18 gnd a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 a 2 nc i/o 0 i/o 1 i/o 2 ce 1 oe a 10 i/o 3 a 1 a 0 a 11 ce 2 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 (a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62128ev30ll automotive-a 2.2 3.0 3.6 45 1.3 2.0 11 16 1 4 cy62128ev30ll automotive-e 2.2 3.0 3.6 55 1.3 4.0 11 35 1 30 notes 1. nc pins are not connected on the die. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 4 of 18 pin definitions i/o type description input a 0 ?a 16 . address inputs input/output i/o 0 ?i/o 7 . data lines. used as input or output lines depending on operation. input/control we . write enable, active low. when selected low, a write is conducted. when selected high, a read is conducted. input/control ce 1 . chip enable 1, active low. input/control ce 2 . chip enable 2, active high. input/control oe . output enable, active low. controls the direction of the i/o pins. when lo w, the i/o pins behave as outputs. when de-asserted high, i/o pins are tr i-stated, and act as input data pins. ground gnd . ground for the device. power supply v cc . power supply for the device. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 5 of 18 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential .......................................?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs in high z state [3, 4] ......................?0.3 v to v cc(max) + 0.3 v dc input voltage [3, 4] ...................?0.3 v to v cc(max) + 0.3 v output current into outputs (low) ............................. 20 ma static discharge voltage ......................................... > 2001 v (mil-std-883, method 3015) latch up current ..................................................... > 200 ma operating range device range ambient temperature v cc [5] cy62128ev30ll automotive-a ?40 c to +85 c 2.2 v to 3.6 v automotive-e ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions 45 ns (auto-a) 55 ns (auto-e) unit min typ [6] max min typ [6] max v oh output high voltage i oh = ?0.1 ma, v cc < 2.70 v 2.0 ? ? 2.0 ? ? v i oh = ?1.0 ma, v cc > 2.70 v 2.4 ? ? 2.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.4 ? ? 0.4 v i ol = 2.1 ma, v cc > 2.70 v ? ? 0.4 ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 v 1.8 ? v cc + 0.3 v v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 v 2.2 ? v cc + 0.3 v v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ?4 ? +4 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ?4 ? +4 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels ?11 16 ?11 35 ma f = 1 mhz ? 1.3 2.0 ? 1.3 4.0 ma i sb1 [7] automatic ce power-down current ? cmos inputs ce 1 > v cc ??? 0.2 v, ce 2 < 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe and we ), v cc = 3.60 v ?1 4?135 ? a i sb2 [7] automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2 v, ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?1 4?130 ? a notes 3. v il(min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc(min) and 200 ? s wait time after v cc stabilization. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 7. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 6 of 18 capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [8] description test conditions 32-pin tsop i 32-pin soic 32-pin stsop unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 33.01 48.67 32.56 c/w ? jc thermal resistance (junction to case) 3.42 25.86 3.59 c/w ac test loads and waveforms figure 4. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 parameters 2.50 v 3.0 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v note 8. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 7 of 18 data retention characteristics over the operating range parameter description conditions min typ [9] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [10] data retention current v cc = 1.5 v, ce 1 > v cc ?? 0.2 v or ce 2 < 0.2 v, v in > v cc ?? 0.2 v or v in < 0.2 v automotive-a ? ? 3 ? a automotive-e ? ? 30 ? a t cdr [11] chip deselect to data retention time 0??ns t r [12] operation recovery time cy62128ev30ll-45 45 ? ? ns cy62128ev30ll-55 55 ? ? data retention waveform figure 5. data retention waveform [13] v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce notes 9. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 10. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 11. tested initially and after any design or process changes that may affect these parameters. 12. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) ? 100 ? s. 13. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 8 of 18 switching characteristics over the operating range parameter [14, 15] description 45 ns (automotive-a) 55 ns (automotive-e) unit min max min max read cycle t rc read cycle time 45 ? 55 ? ns t aa address to data valid ? 45 ? 55 ns t oha data hold from address change 10 ? 10 ? ns t ace ce low to data valid ? 45 ? 55 ns t doe oe low to data valid ? 22 ? 25 ns t lzoe oe low to low z [16] 5?5?ns t hzoe oe high to high z [16, 17] ?18?20ns t lzce ce low to low z [16] 10 ? 10 ? ns t hzce ce high to high z [16, 17] ?18?20ns t pu ce low to power-up 0 ? 0 ? ns t pd ce high to power-down ? 45 ? 55 ns write cycle [18] t wc write cycle time 45 ? 55 ? ns t sce ce low to write end 35 ? 40 ? ns t aw address setup to write end 35 ? 40 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 35 ? 40 ? ns t sd data setup to write end 25 ? 25 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high z [16, 17] ?18?20ns t lzwe we high to low z [16] 10?10?ns notes 14. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 15. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the figure 4 on page 6 . 16. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 17. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 18. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 9 of 18 switching waveforms figure 6. read cycle 1 (address transition controlled) [20, 21] figure 7. read cycle no. 2 (oe controlled) [21, 22, 23] figure 8. write cycle no. 1 (we controlled) [19, 22, 24, 25] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 26 notes 19. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that t erminates the write. 20. the device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 21. we is high for read cycle. 22. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 23. address valid before or similar to ce 1 transition low and ce 2 transition high. 24. data i/o is high impedance if oe = v ih . 25. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 26. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 10 of 18 figure 9. write cycle no. 2 (ce 1 or ce 2 controlled) [27, 28, 29, 30] figure 10. write cycle no. 3 (we controlled, oe low) [27, 30] switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 31 notes 27. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high 28. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that t erminates the write. 29. data i/o is high impedance if oe = v ih . 30. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 31. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 11 of 18 truth table ce 1 ce 2 we oe inputs/outputs mode power hx [32] x x high z deselect/power-down standby (i sb ) x [32] l x x high z deselect/power-down standby (i sb ) l h h l data out read active (i cc ) l h l x data in write active (i cc ) l h h h high z selected, outputs disabled active (i cc ) note 32. the ?x? (don?t care) state for the chip enables in the truth table refer to the logic state (either high or low). intermedia te voltage levels on these pins is not permitted. [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 12 of 18 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62128EV30LL-45SXA 51-85081 32-pin 450 -mil soic (pb-free) automotive-a cy62128ev30ll-45zxa 51-85056 32-pin tsop type i (pb-free) cy62128ev30ll-45zaxa 51-85094 32-pin stsop (pb-free) 55 cy62128ev30ll-55zxe 51-85056 32-pin ts op type i (pb-free) automotive-e cy62128ev30ll-55sxe 51-85081 32-pin 450-mil soic (pb-free) contact your local cypress sales repres entative for availability of these parts. ordering code definitions temperature grade: x = a or e a = automotive-a; e = automotive-e pb-free package type: xx = s or z or za s = 32-pin soic z = 32-pin tsop type i za = 32-pin stsop speed grade: xx = 45 ns or 55 ns ll = low power voltage range: 3 v typical e = process technology 90 nm bus width = 8 density = 1-mbit family code: mobl sram family company id: cy = cypress cy xx xx 621 2 8 v30 x ll x - e [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 13 of 18 package diagrams figure 11. 32-pin molded soic (450 mil) s32.45/sz32.45, 51-85081 51-85081 *c [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 14 of 18 figure 12. 32-pin tsop i (8 20 1.0 mm) z32, 51-85056 package diagrams (continued) 51-85056 *f [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 15 of 18 figure 13. 32-pin small tsop (8 13.4 1.2 mm) za32, 51-85094 package diagrams (continued) 51-85094 *f [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 16 of 18 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable soic small outline integrated circuit sram static random access memory stsop small thin small outline package tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz mega hertz ? a micro amperes ? s micro seconds ma milli amperes ns nano seconds ? ohms % percent pf pico farad v volts w watts [+] feedback
cy62128ev30 mobl ? automotive document #: 001-65528 rev. *a page 17 of 18 document history page document title: cy62128ev30 mobl ? automotive, 1-mbit (128 k 8) static ram document number: 001-65528 rev. ecn no. submission date orig. of change description of change ** 3115909 01/06/2011 rame new datasheet for automotive sram parts. created separate datasheet for automotive sram parts from document no. 38-05579 rev. *h *a 3288690 06/21/2011 rame removed the note ?for best practice recommendations, refer to the cypress application note ?system design guideli nes? at http://www.cyp ress.com.? and its reference in functional description . updated electrical characteristics (test conditions of i sb1 and i sb2 parameters). updated package diagrams . updated in new template. [+] feedback
document #: 001-65528 rev. *a revised june 27, 2011 page 18 of 18 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62128ev30 mobl ? automotive ? cypress semiconductor corporation, 2011. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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